Ukupakishwa okukwinqanaba eliphezulu yenye yeembalasane zetekhnoloji kwixesha le-'More than Moore'.Njengoko iitshiphusi zisiya zisiba nzima kwaye zibiza kakhulu ukwenza i-miniaturise kwindawo nganye yenkqubo, iinjineli zibeka iitshiphusi ezininzi kwiipakethi eziphambili ukuze zingasasokoli ukuzicutha.Eli nqaku linika isingeniso esifutshane kwi-10 yamagama aqhelekileyo asetyenziswa kwi-teknoloji yokupakisha ephezulu.
Iiphakheji ze-2.5D
Iphakheji ye-2.5D yinkqubela phambili yeteknoloji ye-2D IC yokupakisha yendabuko, evumela umgca ococekileyo kunye nokusetyenziswa kwendawo.Kwiphakheji ye-2.5D, iifa ezingenanto zipakishwe okanye zibekwe ecaleni-ngecala phezu kwe-interposer layer kunye ne-silicon nge-vias (TSVs).Isiseko, okanye umaleko we-interposer, ubonelela unxibelelwano phakathi kweechips.
Iphakheji ye-2.5D ngokuqhelekileyo isetyenziselwa i-ASICs ephezulu, i-FPGAs, i-GPUs kunye neekhabhi zememori.Ngo-2008 wabona i-Xilinx yahlula ii-FPGA zayo ezinkulu kwiitshiphusi ezine ezincinci ezinezivuno eziphezulu kwaye ziqhagamshele ezi kumaleko we-silicon interposer.Iiphakheji ze-2.5D zazalwa kwaye ekugqibeleni zasetyenziswa ngokubanzi kwimemori ye-bandwidth ephezulu (HBM) yokudibanisa iprosesa.
Umzobo wepakethe ye-2.5D
Ukupakishwa kwe-3D
Kwiphakheji ye-IC ye-3D, i-logic die ihlanganiswe kunye okanye ngokufa kokugcina, ukuphelisa isidingo sokwakha i-System-on-Chips enkulu (i-SoCs).I-die idityaniswe omnye komnye ngoluhlu olusebenzayo lwe-interposer, ngelixa iipakethe ze-2.5D IC zisebenzisa i-bumps conductive okanye i-TSVs ukupakisha amacandelo kwi-interposer layer, iipakethi ze-3D IC zidibanisa iindidi ezininzi ze-silicon wafers kumacandelo asebenzisa i-TSVs.
Itekhnoloji ye-TSV yeyona nto iphambili iteknoloji eyenza kuzo zombini iiphakheji ze-2.5D kunye ne-3D IC, kwaye ishishini le-semiconductor liye lasebenzisa iteknoloji ye-HBM ukuvelisa iitshiphusi ze-DRAM kwiiphakheji ze-3D IC.
Umbono onqamlezileyo wepakethe ye-3D ubonisa ukuba uqhagamshelo oluthe nkqo phakathi kweetshiphu ze-silicon luphunyezwa ngee-TSV zobhedu zetsimbi.
Chiplet
I-Chiplets yenye indlela yokupakishwa kwe-3D IC eyenza ukudityaniswa okungafaniyo kwe-CMOS kunye namacandelo angekho e-CMOS.Ngamanye amagama, zii-SoCs ezincinci, ezikwabizwa ngokuba zii-chiplets, kunee-SoCs ezinkulu kwiphakheji.
Ukwahlulahlula i-SoC enkulu ibe ziitshiphusi ezincinci, ezincinci zibonelela ngezivuno eziphezulu kunye neendleko eziphantsi kunokufa okungenanto.iichiplets zivumela abaqulunqi ukuba bathathe ithuba loluhlu olubanzi lwe-IP ngaphandle kokuqwalasela ukuba yeyiphi inkqubo yenkqubo ekufuneka isetyenziswe kwaye yeyiphi iteknoloji enokusetyenziswa ukuyivelisa.Banokusebenzisa uluhlu olubanzi lwezixhobo, kubandakanya isilicon, iglasi kunye nelaminates ukwenza itshiphu.
Iinkqubo ezisekwe kwiChiplet zenziwe ngeeChiplets ezininzi kumaleko ophakathi
IiPakethi zeFan Out
Kwiphakheji yeFan Out, "uqhagamshelo" lufefelwe ngaphandle kwendawo yetshiphu ukubonelela nge-I/O yangaphandle engaphezulu.Isebenzisa i-epoxy molding material (EMC) efakwe ngokupheleleyo kwi-die, isusa imfuno yeenkqubo ezifana ne-wafer bumping, i-fluxing, i-flip-chip mounting, ukucoca, ukutshiza phantsi kunye nokunyanga.Ke ngoko, akukho maleko ephakathi efunekayo nokuba, ukwenza udibaniso olungafaniyo lube lula kakhulu.
Itekhnoloji ye-Fan-out ibonelela ngepakethi encinci ene-I/O eninzi kunezinye iintlobo zepakethe, kwaye ngo-2016 yayiyinkwenkwezi yetekhnoloji xa i-Apple yakwazi ukusebenzisa itekhnoloji yokupakisha ye-TSMC ukudibanisa iprosesa yesicelo se-16nm kunye ne-DRAM ephathwayo kwiphakheji enye ye-iPhone. 7.
Ukupakishwa kweFan-out
Ukupakishwa kweNqanaba le-Fan-Out Wafer (FOWLP)
Itekhnoloji ye-FOWLP luphuculo lokupakishwa kwe-wafer-level (WLP) ebonelela ngoqhagamshelo lwangaphandle lweetshiphusi zesilicon.Ibandakanya ukufakela itshiphu kwizinto zokubumba ze-epoxy kwaye emva koko kwakhiwe umaleko wokuxinana okuphezulu kwakhona (i-RDL) kumphezulu we-wafer kunye nokusebenzisa iibhola ze-solder ukwenza i-wafer ephindwe ngokutsha.
I-FOWLP inikezela ngenani elikhulu lokudibanisa phakathi kwepakethi kunye nebhodi yesicelo, kwaye ngenxa yokuba i-substrate inkulu kunokufa, i-die pitch ngokwenene ikhululekile ngakumbi.
Umzekelo wephakheji yeFOWLP
Ukudityaniswa okungafaniyo
Ukudityaniswa kwamacandelo ahlukeneyo awenziwe ngokwahlukileyo kwiindibano zenqanaba eliphezulu kunokuphucula ukusebenza kunye nokuphucula iimpawu zokusebenza, ngoko ke abavelisi becandelo le-semiconductor bayakwazi ukudibanisa amacandelo asebenzayo kunye nenkqubo eyahlukeneyo yokuhamba kwindibano enye.
Ukuhlanganiswa okungafaniyo kufana ne-system-in-package (SiP), kodwa endaweni yokudibanisa i-multiple bare dies kwi-substrate enye, idibanisa ii-IP ezininzi ngendlela ye-Chiplets kwi-substrate enye.Ingcamango esisiseko yokudibanisa okungafaniyo kukudibanisa amacandelo amaninzi anemisebenzi eyahlukeneyo kwiphakheji enye.
Ezinye iibhloko zokwakha zobugcisa kuhlanganiso olwahlukileyo
HBM
I-HBM yitekhnoloji esemgangathweni yokugcina istaki ebonelela ngamajelo aphezulu e-bandwidth yedatha ngaphakathi kwesitaki naphakathi kwememori kunye nezinto ezinengqondo.Iiphakheji ze-HBM zigcina inkumbulo ziyafa kwaye zidibanise kunye nge-TSV ukwenza ngakumbi i-I/O kunye ne-bandwidth.
I-HBM ngumgangatho we-JEDEC odibanisa ngokuthe nkqo iileya ezininzi ze-DRAM ngaphakathi kwephakheji, kunye neeprosesa zesicelo, ii-GPU kunye nee-SoCs.I-HBM iphunyezwe ngokuyintloko njengephakheji ye-2.5D yeeseva eziphezulu kunye neetshiphu zenethiwekhi.Ukukhutshwa kwe-HBM2 ngoku kujongana nomthamo kunye nemida yewotshi yokukhutshwa kwe-HBM yokuqala.
Iiphakheji ze-HBM
Uluhlu oluphakathi
I-interposer layer yi-conduit apho iimpawu zombane zigqithiswa kwi-multi-chip bare die okanye ibhodi kwiphakheji.Lunxibelelwano lombane phakathi kweesokethi okanye iziqhagamshelo, ezivumela imiqondiso ukuba isasazwe kude kwaye idityaniswe nezinye iisokethi ebhodini.
I-interposer layer inokwenziwa nge-silicon kunye nezinto eziphilayo kwaye isebenze njengebhulorho phakathi kwe-multi-die die kunye nebhodi.I-Silicon interposer layers bubuchwephesha obuqinisekisiweyo obunobuninzi bepitch ye-I/O ephezulu kunye nezakhono zokwenza i-TSV kwaye zidlala indima ephambili kwi-2.5D kunye ne-3D IC IC packaging.
Uzalisekiso oluqhelekileyo lwesixokelelwano esahluliweyo somaleko ophakathi
Umaleko wokwabiwa ngokutsha
Umaleko wokwabiwa kwakhona uqulethe udibaniso lobhedu okanye ulungelelwaniso olwenza uxhulumaniso lombane phakathi kwamacandelo ahlukeneyo epakethe.Ingumaleko we-metallic okanye i-polymeric dielectric material enokuthi ifakwe kwi-package kunye ne-bare die, ngaloo ndlela inciphisa i-I / O isithuba se-chipsets ezinkulu.Izahlulo zokwabiwa ngokutsha ziye zaba yinxalenye ebalulekileyo yezisombululo zepakethe ye-2.5D kunye ne-3D, evumela iitshiphusi ezikuzo ukuba zinxibelelane zisebenzisa iileya zomlamli.
Iipakethe ezidityanisiweyo zisebenzisa iileya zokwabiwa kwakhona
TSV
I-TSV iyitekhnoloji ephambili yokuphunyezwa kwe-2.5D kunye ne-3D yokupakisha izisombululo kwaye i-wafer ezaliswe lubhedu ebonelela ngokudibana okuthe nkqo nge-silicon wafer die.Ihamba ngedayiti yonke ukubonelela ngoqhagamshelo lombane, yenze eyona ndlela imfutshane ukusuka kwelinye icala lokufa ukuya kwelinye.
Ngemingxuma okanye vias zichotshelwe ubunzulu obuthile ukusuka kwicala langaphambili le-wafer, ethi emva koko igqunywe kwaye izaliswe ngokufaka izinto eziphathekayo (ngokuqhelekileyo ubhedu).Emva kokuba itshiphu yenziwe, iyancipha ukusuka kwicala elingasemva le-wafer ukuze iveze i-vias kunye nentsimbi efakwe kwicala elingasemva le-wafer ukugqiba i-TSV interconnect.
Ixesha lokuposa: Jul-07-2023